The present invention relates to the field of integrated circuits and relates more particularly to the architecture of a programmable interconnection device and to the application of such a device to programmable logic circuits such as field-programmable gate network (FPGA) components.
A programmable interconnection device (or system) comprises an electronic circuit enabling interconnection functions to be established between N outputs and M inputs (where N and M are natural integers). Such a programmable interconnection device can thus be connected between the N outputs of a first set of electronic circuits and the M inputs of a second set of electronic circuits so as to establish programmatically the logical connections between a subset of the M outputs of the first set of circuits and a subset of the N inputs of the second set of circuits.
The interconnection function allocates a single output of the first set to each input of the second set. In contrast there is no limit on the number of inputs of the second set that may receive a given output of the first set.
In a manner known, an FPGA circuit is a logic integrated circuit having individual logic blocks that can be assembled together freely. These logic blocks are interconnected with one another using programming, either permanently or reversibly, in order to implement the desired function(s).
A single FPGA circuit can thus be used in different electronic applications. After being programmed, the FPGA circuit behaves like an application specific integrated circuit (ASIC) implementing the logic function(s) established by the programming.
By way of example, a logic block may include a correspondence table or look-up table (LUT) and a “flip-flop”.
An FPGA circuit may be organized as a large number of functional blocks, each functional block having a plurality of individual logic blocks so as to be capable of performing particular functions. Like the individual logic blocks, these functional blocks are interconnected by a routing matrix that can be configured by programming. This matrix enables the FPGA component to be reconfigured at will.
FIG. 1 is a diagram of a conventional architecture known as “Manhattan” (or two-dimensional (2D)) for a programmable interconnection circuit 2 in which the logic blocks BL are positioned regularly in rows and columns. The programmable interconnections are made by sets of horizontal and vertical conductor tracks HR and VR, and by switch blocks SW suitable for making programmable interconnections between said conductor tracks. The switch blocks SW are regularly arranged in rows and columns so as to be interleaved between the rows and columns of the logic blocks BL.
The type of network shown in FIG. 1 nevertheless requires a large number of conductors and thus a large amount of space for providing sufficient effectiveness. The term “effectiveness” is used to mean the ability of a structure to be programmed to reproduce the interconnections needed for a given application without blocking and regardless of complexity.
A “Manhattan” network becomes relatively ineffective and bulky as the number of logic blocks increases. Although it is true that propagation times in such networks are generally acceptable for logic blocks that are spatially close together, it should nevertheless be observed that such propagation times become less and less satisfactory as the distance between logic blocks increases, with this being explained in particular by the increasing number of switch blocks SW through which it is necessary to pass in order to convey a signal.
FIG. 2 shows a known architecture for another programmable interconnection circuit 4 in which the logic blocks BL are grouped together as a plurality of sets EH1 in a first hierarchical level. By way of example, each set EH1 may constitute a functional block.
In this example, the logic blocks BL are interconnected by a network of matrices X1 referred to as “crossbars”, these matrices serving to provide interconnections between the logic blocks BL and the inputs/outputs of the first hierarchical level.
The sets EH1 of the first hierarchical level are grouped together in a plurality of sets EH2 at a second hierarchical level. The sets EH1 are interconnected by a network of crossbars X2 providing connections between the sets EH1 and the inputs/outputs of the second hierarchical level. The circuit 4 may have as many hierarchical levels as necessary.
Once the number of logic blocks BL becomes very large, the architecture of the circuit 4 is more effective and more compact than the “Manhattan” structure shown in FIG. 1.
The propagation time characteristics of the circuit 4 are also satisfactory within a given hierarchical level, but they are severely penalized by the fact that the connections between two distinct sets within the same hierarchical level need to pass via the higher hierarchical level. Thus, two logic blocks BL can be spatially close together on the chip but far apart in time in terms of signal propagation because the two logic blocks belong to two distinct hierarchical sets.
There thus exists a need for a programmable interconnection device that presents satisfactory performance, in particular in terms of effectiveness, of signal propagation time, and of compactness on the chip.